The present exemplary embodiments pertain to semiconductor processing and, more particularly, pertain to exemplary embodiments of semiconductor processing in which there is aggressive tip-to-tip scaling using subtractive integration.
Semiconductor structures are being developed in which feature sizes are continually being decreased. The problems caused by tight tip-to-tip contact spacing are particularly severe in highly integrated circuits with the greatest demand for feature size reduction and scaling. Feature size reduction may be even more acute as feature size reduction approaches 10 nanometer (nm) and beyond.